The present invention relates to a semiconductor device having an insulated gate. The present invention is applicable to a power MOSFET (Metal-Oxide-Silicon Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a thyristor.
A power MOSFET having low ON-resistance was previously proposed by the present inventor. As shown in FIG. 14, the power MOSFET is has an n+-type substrate J1 making up an n+-type drain region and, an n−-type drift region J5, a p-type base layer J4, an n+-type source layer J3, and a plurality of gate electrodes J2. The gate electrodes J2 are plate-like and are embedded upright in the power MOSFET to divide the p-type base layer J4 and the n+-type source layer J3 into a plurality of p-type base regions J4 and a plurality of n+-type source regions J3, respectively. With this structure, channels are formed to extend in the lateral direction of FIG. 14.
The power MOSFET shows especially low ON resistance in the range between low and medium breakdown voltage. For example, when each gate electrode J2 has a depth of 30 micrometers, the power MOSFET has a correlation shown in FIG. 15 between normalized ON resistance and breakdown voltage. The power MOSFET has a lower normalized ON resistance than the theoretical limit of a vertical DMOS (double-diffused MOS) in the breakdown voltage range between about 40 and 300 V.
The power MOSFET described above is manufactured in the manner shown in FIGS. 16A to 16E. As shown in FIG. 16A, a silicon oxide film J6 formed on a surface of the substrate J1 is defined using photolithography. The substrate J1, when masked by the defined film J6, is etched to form a trench J7, as shown in FIG. 16B. The trench J7 is filled with the n−-type drift region J5, the p-type base layer J4, and the n+-type source layer J3 in this order using an epitaxial growth technique, as shown in FIGS. 16C and 16D. Afterward, the three layers above the level of the silicon oxide film J6 are removed. Although not illustrated, the power MOSFET is completed with the following steps or steps similar to the following steps. A plurality of trenches are formed to divide the p-type base layer J4 and the n+-type source layer J3 into a plurality of n+-type source regions J3 and a plurality of p-type base regions J4, respectively. A gate oxide layer is formed on the surface defining each trench. Then, each trench is filled with the gate electrode J2.
After the trench J7 is filled with the layer J3, a crystalline defect or void tends to occur in the trench J7 because the surface of the layer J3 grows inwardly from the sidewall of the trench J7 and joins, or meets itself, in the trench J7. If the crystalline defect or void is generated in the proximity of the gate oxide layer, the breakdown voltage of the gate is reduced. FIG. 17 shows a structural modification, in which each gate electrode J2 is divided in two and the n+-type source layer J3 is widened. This modification prevents the breakdown voltage from being reduced by the crystalline defect. However, this modification enlarges the size of the device and decreases the area of the channel. The normalized ON resistance increases due to the decreased area of the channel.
In addition, the p-type base layer J4 is formed in the lightly-doped n−-type drift region J5 in the proposed power MOSFET, so the electric field is unfavorably concentrated at the bottom corner of the layer J4, as shown in FIG. 18, which is a simulation of electric field distribution when 80 V is applied to the drain.